An example of a prior art digital VTR will hereinafter be described with reference to FIGS. 1 to 3. In the first place, an arrangement relationship of rotary magnetic heads of the prior art digital VTR will be described with reference to FIG. 1. Reference letter DR designates a tape guide drum which is constituted by a rotary drum as an upper drum and a fixed drum as a lower drum. This tape guide drum DR may be formed of a fixed drum as an upper and lower drum and a rotary drum as a middle drum. Reference letters H.sub.A to H.sub.D designate recording rotary magnetic drums and H.sub.A ' to H.sub.D ' designate reproducing rotary magnetic heads. Each of these rotary magnetic heads is mounted on the rotary drum of the tape guide drum DR with an arrangement relationship that will be described below. The recording rotary magnetic heads H.sub.A, H.sub.B and H.sub.C, H.sub.D are two pairs of recording rotary magnetic heads disposed with an angular spacing of 180.degree., while the reproducing rotary magnetic heads H.sub.A ', H.sub.B ' and H.sub.C ', H.sub.D ' are two pairs of reproducing rotary magnetic heads disposed with an angular spacing of 180.degree.. The lines connecting these two pairs of reproducing rotary magnetic heads and two pairs of recording rotary magnetic heads are perpendicular to each other. The recording rotary magnetic heads H.sub.A and H.sub.B are adapted to record a digitized video signal so as to form magnetic tracks each having a different azimuth on a magnetic tape TP, while upon reproducing the reproducing rotary magnetic heads H.sub.A ' and H.sub.B ' are adapted to reproduce the recorded signals on the respective tracks. Similarly, the recording rotary magnetic heads H.sub.C and H.sub.D are adapted to record a digitized video signal so as to form magnetic tracks each having a different azimuth on the magnetic tape TP, while upon reproducing, the reproducing rotary magnetic heads H.sub.C ' and H.sub.D ' are adapted to reproduce the signals recorded on these tracks.
References TG.sub.1 and TG.sub.2 designate tape guide poles for determining a wrapping angle .theta. with which the magnetic tape TP is wound around the tape guide drum DR. The tape wrapping angle .theta. is selected to be, for example, 240.degree..
Now, a recording system of the prior art digital VTR will be described with reference to FIG. 2. Reference numeral 1 designates an A/D converter to which component color video signals, i.e., a luminance signal Y, a blue color difference signal B-Y and a red color difference signal R-Y are supplied and thereby A/D-converted to be digital component video signals. These digitized component video signals are supplied to a multiplexer 2, in which they are multiplexed and 2-channel encoded and thereby produced as 2-channel multiplexed digital video signals. These signals are supplied to a shuffle or interleaving circuit 3 provided with a memory and thereby shuffled. In this shuffle circuit 3, the 2-channel digital video signals are written in the memory by respective write clock pulses and then read out therefrom by respective read clock signals at a predetermined processing speed, whereby to shuffle the 2-channel digital video signals, thus preventing a burst error from occurring in a reproduced data due to the dropout of the tape and so on.
The 2-channel digital video signals derived from the shuffle circuit 3 are supplied to an error correcting and encoding circuit 4 in which they are encoded and then fed to a time base expanding circuit (FIFO memory) 5 and thereby time-base-expanded. In the time base expanding circuit 5, the 2-channel digital video signals from the error correcting and encoding circuit 4 are written in a memory by a write clock signal corresponding to the processing speed and then read out therefrom by a read clock signal corresponding to the recording rate.
The 2-channel digital video signals derived from the time base expanding circuit 5 are alternately supplied to recording amplifiers 6A, 6B and 6C, 6D at every 1/5 field (or at every 1/6 field). The respective outputs from the recording amplifiers 6A, 6B and 6C, 6D are respectively supplied to the recording rotary magnetic heads H.sub.A, H.sub.B and H.sub.C, H.sub.D and thereby recorded on the magnetic tape TP so as to form slant tracks.
A reproducing system of the prior art digital VTR will be described with reference to FIG. 3. The digital video signals reproduced from the magnetic tape TP by the reproducing rotary magnetic heads H.sub.A ' to H.sub.D ' are respectively supplied through playback amplifiers 7A, 7B, 7C and 7D to playback processors 8A, 8B, 8C and 8D each having a PLL and a bit synchronizing circuit. In these playback processors 8A to 8D, the reproduced digital video signals from the respective amplifiers 7A to 7D are supplied to the PLLs and thereby the clock signals are detected. By these clock signals, the respective digital video signals supplied to the bit synchronizing circuits are synchronized. Further, the playback processors 8A to 8D include extracting circuits for extracting block synchronizing signals from the synchronized digital video signals on the basis of the output signals from the bit synchronizing circuits and the PLLs.
The outputs from the playback processors 8A to 8D are supplied to a time base corrector 9 in which they are time-base-compressed. In this time base corrector 9, the outputs from the playback processors 8A to 8D are written in a memory by a write clock signal corresponding to a recording rate and then read out therefrom by a read clock signal corresponding to the processing speed to thereby time-base-compress the same. The time-base-compressed 2-channel digital video signals derived from the time base corrector 9 are supplied through a synchronizing detector circuit 10 to an address reproducing circuit 11. The 2-channel digital video signals derived from the address reproducing circuit 11 are supplied to an error correcting decoder 12 in which they are error-corrected and then supplied to and written in a frame memory 13.
The 2-channel digital video signals read out from the memory 13 are supplied to a de-shuffle de-interleave circuit 14. In the de-shuffle circuit 14, the 2-channel digital video signals from the memory 13 are written by a write clock signal based on the write processing speed and de-shuffled and read out therefrom by a read clock signal corresponding to a read processing speed, so that even if the burst error occurs in the reproduced signal due to a dropout or the like, there is a small possibility that errors will occur together on the picture.
The 2-channel digital video signals from the de-shuffle circuit 14 are supplied to a de-multiplexer 15 in which they are decoded to 3-channel digital component video signals. Thereafter, they are fed to an error concealing circuit 16 and thereby error-concealed. The 3-channel digital component video signals from the error concealing circucit 16 are supplied to a D/A converter 17 in which they are D/A-converted and thereby developed as analog component video signals, that is, the luminance signal Y, the blue color difference signal B-Y and the red color difference signal R-Y.
The method for error-concealing the digital video data in the prior art digital VTR will be described with reference to FIGS. 4 to 9.
FIG. 4 illustrates a desired picture element e on a desired scanning line L.sub.n on the video screen of a television receiver and 8 adjacent picture elements a to d and f to i on the same scanning line L.sub.n adjacent the desired picture element and on the upper and lower scanning lines L.sub.n-1 and L.sub.n+1. In this case, between two picture elements adjacent on the upper and lower scanning lines of the video screen, for example, picture elements a and d there is a time difference of one horizontal period (1H).
When the data corresponding to the picture element e must be error-concealed, the data is interpolated by one of the data of picture elements adjacent to the picture element e in the left and right hand sides (d, f), in the upper and lower sides (b, h), in the oblique directions (a, i; c, g), in the cross-form (b, d, f, h) and x-form (a, c, g, i) or is substituted with the data corresponding to any one of the ambient picture elements.
A prior art error concealing apparatus will be described with reference to FIG. 5. In FIG. 5, reference numeral 20 designates an overall arrangement of a delay memory. Since 9 picture elements of square lattice extending to, for example, three scanning lines shown in FIG. 4 are to be processed, the full delay time of the delay memory 20 is set as 2H+2T.sub.S where T.sub.S is the delay time for one picture element (sample unit) and H is the horizontal period. Reference numerals 21 to 28 designate individual delay elements, respectively and reference numeral 29 designates an error concealing circuit. A digital video data signal applied to an input terminal IN was already error-corrected. If the error of this digital video signal is beyond the error correction ability, such digital video data signal accompanying with an error flag is supplied to the first unit delay memory 21 and also branched to and supplied to the error concealing circuit 29. The output from the first unit delay memory 21 is supplied to the second unit delay memory 22 and also branched to and supplied to the error concealing circuit 29. Reference numeral 23 designates a main delay memory and the delay time thereof is selected to be equal to a time difference (1H-2T.sub.S) between the picture element f on the right-hand side of one scanning line L.sub.n and the picture element g at the left-hand side of the succeeding scanning line of the square lattice shown in FIG. 4. The output from the second unit delay memory 22 is supplied to the main delay memory 23 and also branched to and fed to the error concealing circuit 29. The delay memories 24 to 26 have delay times the same as those of the above mentioned delay memories 21 to 23. The output from the first main memory 23 is sequentially supplied through the third and fourth unit delay memories 24 and 25 to the second main memory 26 and the outputs from the respective delay memories 24 to 26 are also branched to and then fed to the error concealing circuit 29. Reference numerals 27 and 28 designate fifth and sixth unit delay memories. The output from the second main delay memory 26 is sequentially supplied to both the unit delay memories 27 and 28 and the outputs from both the unit delay memories 27 and 28 are supplied to the error concealing circuit 29. The error concealing circuit 29 uses the respective digital video data derived from the delay memory 20 to carry out concealing processings, such as, determining the optimum interpolation direction and so on. The digital video data error-concealed therein is led out at an output terminal OUT. When the input digital video data does not require the error-concealment, the input digital video data is merely passed through the error concealing circuit 29 and then developed at the output terminal OUT as it is.
At the center of the delay memory 20, or the connection point between the third and fourth unit delay memories 24 and 25 or at time point t.sub.0 in which a data .circle.e corresponding to the central picture element e of the square lattice shown in FIG. 4 exists, data at the input and output terminals of the delay memory 20 and at the respective branching points thereof become .circle.i to .circle.a corresponding to the respective picture elements i to a in the direction from the input terminal to the output terminal.
FIG. 6 illustrates patterns of the recording tracks formed on the magnetic tape TP by the afore mentioned digital VTR, in which A, B, C and D respectively designate slant tracks recorded by the recording rotary magnetic heads H.sub.A, H.sub.B, H.sub.C and H.sub.D which are sequentially suffixed as 0, 1, 2, . . .
Reference A', B', C' and D' respectively designate tracing tracks in a case where the magnetic tape TP is transported at the constant and same speed as that of the recording mode and the respective tracks are traced by the corresponding reproducing rotary magnetic heads H.sub.A ', H.sub.B ', H.sub.C ' and H.sub.D ' to thereby reproduce the recorded signals. These references A', B', C' and D' are suffixed as 0, 1, 2, . . . In this case, since these tracing tracks are substantially completely coincident with the recording tracks, the amplitudes of the envelopes of the respective reproduced high frequency signals are made substantially constant on the whole of each tracing track by the respective reproducing rotary magnetic heads H.sub.A ' to H.sub.D '.
Since as earlier noted the digital VTR carries out the shuffling operation upon recording, it is rare that errors will occur together on the video screen upon playback mode with constant tape speed. Accordingly, even if the error occurs in the data corresponding to the picture element e in FIG. 4, the data corresponding to the nearby picture elements a to d and f to i can be used for the error concealing processing in their original conditions.
However, when the magnetic tape TP similar to FIG. 6 is transported at high speed, for example, at a tape transport speed three times the transport speed of the recording mode, the patterns of the tracks A.sub.1 ', B.sub.1 ', C.sub.1 ', D.sub.1 ', A.sub.2 ', B.sub.2 ', . . . traced by the reproducing rotary magnetic heads H.sub.A ' to H.sub.D ' become as shown in FIG. 7. Since the respective magnetic heads alternately intersect the recording tracks having different recording azimuths a large number of times, the envelope at every track of each reproduced high frequency signal by the reproducing rotary magnetic heads H.sub.A ' to H.sub.D ' becomes a waveform in which a lozenge is repeatedly formed as shown in FIG. 8. Since such reproduced high frequency signal can be used only in its portion (the hatched area in FIG. 8) where the amplitude thereof is higher than a predetermined value, the desired reproduced data can not be obtained. Accordingly, if an error occurs in a data near a data to be concealed a reproduced data can not be obtained and so on, so that the error concealment using the nearby data can not be made. In this case, the quality of the reproduced picture is deteriorated.
Although as shown in FIG. 9 it may be considered that the sampling range of the concealing data is enlarged, this urges the circuit scale to be increased considerably and is neither economical nor easily realizable. FIG. 9 illustrates a desired picture element e on a desired scanning line L.sub.n and 24 adjacent picture elements a to d, f to i and j to y on the same scanning line L.sub.n and upper and lower two of scanning lines L.sub.n-2, L.sub.n-1 ; L.sub.n+1, L.sub.n+2 of the video screen of the television receiver. In this case, however, let it be assumed that data corresponding to the picture elements a to i be erroneous and that data corresponding to the remaining picture elements is correct. By the interpolation or delay by using the data of the picture elements selected from the 24 picture elements, the data corresponding to the picture element e is error-concealed.
In view of such aspects, an object of this invention is to provide an error concealing system for digital data by which in a reproducing system having a relatively high error rate, the concealing processing can be carried out by using an error-concealing data of small scale.